High-speed digital logic circuits rely on digital clock signals with low timing uncertainty or jitter (both deterministic and random). Generally, digital clock signals are generated by a clock generator including a phase-locked loop (PLL) and voltage (or current) controlled oscillator (VCO). The PLL output includes a phase and frequency which is used to lock the VCO to a low-jitter external reference oscillator clock signal (reference clock source). One of the main contributors to digital clock jitter in such a clock generator is noise on the power supply voltage signal to the PLL and VCO. A dedicated or “clean” power supply voltage signal is not always available. The PLL and VCO may be forced to share a common power supply voltage signal with other logic blocks that inject digital switching activity (noise) into the common power supply voltage signal.
In the absence of a dedicated “clean” power supply voltage input to a PLL-VCO based clock generator, it is highly desirable to generate a “clean” power supply voltage signal. One technique is to filter and/or voltage regulate an existing noisy power supply voltage signal using a low dropout voltage regulator (LDO). The output of the LDO is used to power the VCO and PLL in the clock generator, as these circuit blocks are particularly sensitive to power supply voltage noise. There are several known LDO implementations suitable for PLL-VCO clock generator applications. These typically involve using one or more voltage regulator stages to reduce noise coupling.
Traditionally, integrated circuits (ICs) incorporating an on-chip PLL and VCO use independent power-supply bumps to achieve a clean power supply connection. The number of power-supply bumps and silicon die bond pads increases as multiple PLLs and VCOs are incorporated into the IC. The power-supply bumps refer to a solder ball connection between a packaged IC and the main application circuit board. By incorporating LDOs on an IC in order to support applications requiring low jitter, the number of power-supply and ground connections can be minimized, thereby reducing the packaged IC pin count, chip and main application circuit board routing complexity.
FIG. 1 shows a schematic diagram of a conventional oscillatory system 10. Oscillatory system 10 includes LDO 20, reference clock source 30, and PLL-VCO clock generator 40. LDO 20 further includes capacitive voltage booster 120 for powering PLL-VCO clock generator 40. LDO 20 regulates an input voltage, VDD_NOISY, to generate a “clean” regulated output voltage (first input bias voltage), VDD_REG, into PLL-VCO clock generator 40. VDD_REG feeds into noise sensitive PLL 160 and VCO 170 contained within PLL_VCO clock generator 40. PLL_VCO clock generator 40 also receives reference clock, REF_CLK, from reference clock oscillator 30. Reference clock oscillator 30 provides a stable clock source to lock the output of VCO 170 to a desired output signal, VCO_CLK, which in the example figure is at frequency, Fosc.
Referring to FIG. 1, PLL 160 compares input clocks, REF_CLK and VCO_CLK to generate voltage control signal, Vctrl, which operates to phase-frequency lock VCO 170. There are other known implementations for constructing PLL 160 depending on required frequency resolution (frequency step-size) for oscillatory system 10 as well as the operating frequency range (low-speed digital, high-speed digital, or radio frequency, and the like).
Capacitive voltage booster 120 is in series with a RC low-pass filter (comprised of resistor Rf 130 and capacitor Cf 140) to generate a signal, GATE_BOOST, which voltage level is higher than that of VDD_NOISY. GATE_BOOST biases the gate of a source-follower voltage regulator comprised of NMOS transistor 150. Here, GATE_BOOST must be higher than VDD_NOISY to ensure NMOS transistor 150 is in saturation while maintaining a low voltage drop between the input VDD_NOISY and an output signal of LDO 20, VDD_REG.
Configured this way, LDO 20 provides reasonable noise isolation between VDD_NOISY and VDD_REG across a wide frequency range. However, GATE_BOOST (ideally a DC voltage) also has an AC voltage component or “ripple” which is an artifact of the switching activity (clocked by REF_CLK in this instance) generated by capacitive voltage booster 120. Large component values for resistor Rf 130 and capacitor Cf 140 (RC filtering) are typically used to minimize the AC voltage component of GATE_BOOST before applying it to the gate of NMOS transistor 150. Any voltage fluctuations at the gate of NMOS transistor 150 tend to appear at the source node, which corresponds to signal, VDD_REG, into PLL 160 and VCO 170.
Although LDO 20 isolates VDD_NOISY from VDD_REG, VDD_REG includes a voltage ripple component from REF_CLK which is input into capacitive voltage booster 120. This voltage ripple component injects noise into VCO 170 output clock signal, VCO_CLK. In this instance, VCO_CLK shows deterministic jitter in the time domain or spurs (at intervals of FREF—CLK) in the frequency domain. Both effects are undesirable depending upon the target application. One option is to replace LDO 20 with a switching voltage regulator; however, a voltage ripple component is again introduced resulting in deterministic jitter at VCO_CLK.
For applications requiring low oscillator phase noise, such as (i) many analog and radio frequency oscillatory systems, particularly in high-speed digital designs (multi-GHz CPUs, digital communication links, and the like) as well as (ii) radio frequency and analog frequency synthesizer designs (transmitters, receivers, signal generators, and the like), improved low jitter oscillatory systems are desired.
The appended drawings illustrate exemplary configurations of the disclosure and, as such, should not be considered as limiting the scope of the disclosure that may admit to other equally effective configurations. Correspondingly, it has been contemplated that features of some configurations may be beneficially incorporated in other configurations without further recitation.